1. Technical Field
This patent relates to a semiconductor device, and, more particularly, to a semiconductor device which can finely control various signals used in the semiconductor device using a simple configuration including a decoder for controlling conditions of the signals possibly given in controlling the timings of the signals, a decoder for controlling the timing of each signal, and fuse units for controlling the decoders, respectively.
2. Description of the Related Art
Generally, in a semiconductor device, input data input to the semiconductor device from the external of the semiconductor device is controlled in setup/hold time before being latched in accordance with a data strobe signal. The data latched in synchronism with the data strobe signal is re-latched in synchronism with a clock controlled in DQSS time. The resultant data is then transmitted via a global data bus line. Here, “strobe signal” generally means a control signal used for data transmission. Such a strobe signal is a short pulse signal which is usable in a computer system to achieve synchronization of data transmission. The above-mentioned data strobe signal means a signal which is used to control inputting of data such that the data is input in synchronism with rising and falling edges thereof. Also, “DQSS time” means a delay time from a rising edge of a clock, at which a write command is input, to a first rising edge of a DQS signal, namely, a data strobe signal. That is, the DQSS time is a timing margin between the data strobe signal and the clock. Generally, the above-mentioned setup/hold time and DQSS time are limited to certain ranges, respectively. For example, allowable ranges of the setup/hold time and DQSS time are stipulated in a specification of the Joint Electron Device Engineering Council (JEDEC) standard.
FIG. 1 is a block diagram illustrating a configuration of a conventional semiconductor device. A data input operation of the conventional semiconductor device will be described with reference to FIG. 1.
As shown in FIG. 1, input data DQ, which is input from the external of the semiconductor device, is buffered by a DQ buffer 112, and is then applied to a delay 132. The delay 132 is adapted to control the setup/hold time of the input data DQ buffered by the DQ buffer 1112. The delay 132 controls the delay time of the input data DQ in accordance with fuse signals respectively output from fuse units 121 to 124. That is, when test mode signals TM0 to TM3 are input to the fuse units 121 to 124, respectively, in a predetermined test mode, an appropriate delay time for controlling the setup/hold time of the input data DQ is determined. Based on the determined delay time, a selected one or ones of the fuses of the fuse units 121 to 124 are cut to determine a desired combination of fuse signals output from the fuse units 121 to 124. In accordance with the fuse signals output from the fuse units 121 to 124, the delay 132 controls the delay time, thereby controlling the setup/hold time.
A data strobe signal DQS is input to a DQS buffer 111 which, in turn, buffers the input data strobe signal DQS. The buffered data strobe signal DQS is applied to a delay 131 which, in turn, outputs the data strobe signal DQS after a predetermined delay time.
In synchronism with the data strobe signal DQS output from the delay 131, a latch 140 latches the delayed input data output from the delay 132, and outputs the resultant aligned input data ALIGN_DATA.
Meanwhile, a clock CLK is input to a clock buffer 113 which, in turn, buffers the input clock CLK. The buffered clock CLK is applied to a delay 133 which, in turn, outputs the clock CLK after a predetermined delay time, namely, a delayed clock CLKD. The delay 133 is adapted to control a DQSS time between the clock CLK buffered by the clock buffer 112 and the data ALIGN_DATA. The delay 133 controls the delay time of the clock CLK in accordance with fuse signals respectively output from fuse units 125 to 128. That is, when test mode signals TM4 to TM7 are input to the fuse units 121 to 124, respectively, in a predetermined test mode, an appropriate delay time for controlling the DQSS time is determined. Based on the determined delay time, a selected one or ones of the fuses of the fuse units 125 to 128 are cut to determine a desired combination of fuse signals output from the fuse units 125 to 128. In accordance with the fuse signals output from the fuse units 125 to 128, the delay 133 controls the delay time, thereby controlling the DQSS time.
The data ALIGN_DATA is latched by a latch 150 in synchronism with the delayed clock CLKD. The latch 150 transmits the latched data, namely, data WGIO, via a global data bus line.
In the above-mentioned conventional semiconductor device, however, there is a problem in that the circuit for controlling the timing of each signal used in the semiconductor device may be complicated as the number of possible conditions of the signal increases. As mentioned above, the conventional semiconductor device includes separate fuse units which are adapted to control individual signals whose timing is to be controlled, respectively. For this reason, when the number of signals to be controlled increases, the number of the fuse units must correspondingly be increased, thereby causing the circuit to be complicated. Furthermore, since each fuse unit is limitedly used, namely, is only used for a particular signal. For this reason, there is a problem in that the utility of the fuse unit is degraded. In addition, there is a problem in that the accuracy of the semiconductor device in controlling the timing of each signal per fuse unit is more or less inferior.